1. Field of the Invention
This invention relates to a quick chamber seal design. More particularly, this invention relates to quick chamber seals for sealing a wafer stage chamber assembly in a photolithography process to manufacture semiconductor wafers.
2. Description of the Related Art
In manufacturing integrated circuits using photolithography, light is transmitted through non-opaque portions of a pattern on a reticle, or photomask, through a projection exposure apparatus, and onto a wafer of specially-coated silicon or other semiconductor material. The uncovered portions of the coating, that are exposed to light, are cured. The uncured coating is then removed by an acid bath. Then, the layer of uncovered silicon is altered to produce one layer of the multi-layered integrated circuit. Conventional systems use visible and ultraviolet light for this process. Recently, however, visible and ultraviolet light have been replaced with electron, x-ray, and laser beams, which permit smaller and more intricate patterns.
As the miniaturization of a circuit pattern progresses, the focus depth of the projection exposure apparatus becomes very small, making it difficult to align accurately the overlay of circuit patterns of the multi-layered integrated circuit. As a result, a primary consideration for an overall design of the photolithography system includes building components of the system that achieve precision by maintaining small tolerances. Any vibration, distortion, or misalignment caused by internal, external or environmental disturbances must be kept at minimum. When these disturbances affect an individual part, the focusing properties of the photolithography system are collectively altered.
In a conventional exposure apparatus of a photolithography system, a wafer stage device is used in combination with a projection lens assembly to manufacture semiconductor wafers. The wafer stage device includes a wafer table to support the wafer substrates, a wafer stage to position the wafer substrates as the wafer stage is being accelerated by a force generated in response to a wafer manufacturing control system, and a wafer stage base to support the wafer stage. The wafer manufacturing control system is the central computerized control system executing the wafer manufacturing process. To permit smaller and more intricate circuit patterns, the projection lens assembly must accurately focus the energy beam to align the overlay of circuit patterns of the multi-layered integrated circuit. The photolithography process of the conventional exposure apparatus is performed with the semiconductor substrates exposed to an atmospheric condition.
A recent development of the photolithography process indicates that the semiconductor substrates need to be processed in a controlled environment which contains a controlled atmosphere, such as nitrogen or helium, to meet certain wafer manufacturing specifications and to improve the quality of the resulted wafers. Therefore, there is a need for a wafer stage chamber design to isolate the semiconductor substrates, the wafer stage device, and the process of making thereof from the atmospheric condition.
The advantages and purposes of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The advantages and purposes of the invention will be realized and attained by the elements and combinations particularly pointed out in the appended claims.
To attain the advantages and consistent with the principles of the invention, as embodied and broadly described herein, a first aspect of the invention is a chamber seal device for sealing a wafer stage chamber assembly of a photolithography system for manufacturing semiconductor substrates. The wafer stage chamber assembly has a first portion and a second portion. The chamber seal device comprises a plurality of pins, at least one keyhole strip, and an o-ring seal. The plurality of pins are aligned on a first flange surrounding a perimeter of the first portion for insertion into a corresponding plurality of openings on a second flange surrounding a perimeter of the second portion. Each of the plurality of pins has a pinhead. The at least one keyhole strip is for insertion into at least a portion of the plurality of pinheads to slidably lock the plurality of pins fastening at least a portion of the first and second flanges to construct the wafer stage chamber assembly. The o-ring seal is positioned in between and surrounding the perimeter of the first and second flanges to seal the wafer stage chamber assembly.
A second aspect of the present invention is a chamber seal device for sealing a wafer stage chamber assembly of a photolithography system for manufacturing semiconductor substrates. The wafer stage chamber assembly has a first portion and a second portion. The chamber seal device comprises at least one clamp channel and at least one o-ring seal. The at least one clamp channel fastens at least a portion of a perimeter of a first flange of the first portion with a corresponding portion of a second flange of the second portion. The at least one o-ring seal is positioned in between and surrounding the perimeter of the first and second flanges to seal the wafer stage chamber assembly.
A third aspect of the present invention is a wafer stage chamber assembly of a photolithography system for manufacturing semiconductor substrates. The wafer stage chamber assembly comprises a chamber portion having a first flange surrounding a perimeter of the chamber portion, and a top wall having a second flange surrounding a perimeter of the top wall. The second flange has a plurality of openings. The wafer stage chamber assembly also comprises a plurality of pins aligned on the first flange for insertion into the plurality of openings on the second flange. Each of the plurality of pins has a pinhead. Further, the wafer stage chamber assembly comprises at least one keyhole strip for insertion into at least a portion of the plurality of pinheads to slidably lock the plurality of pins fastening at least a portion of the first and second flanges to construct the wafer stage chamber assembly, and an o-ring seal positioned in between and surrounding the perimeter of the first and second flanges to seal the wafer stage chamber assembly.
A fourth aspect of the present invention is a wafer stage chamber assembly of a photolithography system for manufacturing semiconductor substrates. The wafer stage chamber assembly comprises a chamber portion having a first flange surrounding a perimeter of the chamber portion, and a top wall having a second flange surrounding a perimeter of the top wall. The wafer stage chamber assembly also comprises at least one clamp channel to fasten at least a portion of the perimeter of the first flange with a corresponding portion of the second flange, and at least one o-ring seal positioned in between and surrounding the perimeter of the first and second flanges to seal the wafer stage chamber assembly.
A fifth aspect of the present invention is a wafer stage chamber assembly of a photolithography system for manufacturing semiconductor substrates. The wafer stage chamber assembly comprises a chamber portion having a U-shaped clamp surrounding a perimeter of the chamber portion, and a top wall having a flange surrounding a perimeter of the top wall. The flange is fitted for engagement with the U-shaped clamp. The wafer stage chamber assembly also comprises at least one o-ring seal positioned between one leg of the U-shaped clamp and the flange surrounding the perimeter of the chamber portion and the top wall to seal the wafer stage chamber assembly.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. Additional advantages will be set forth in the description which follows, and in part will be understood from the description, or may be learned by practice of the invention. The advantages and purposes may be obtained by means of the combinations set forth in the attached claims.